Daniel C. Johnson

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Privately Held Company (9/1/2011 to present - Louisville, KY)

R&D Engineering Manager - Developing a wide range of embedded devices in support of various R&D and product development projects. I also design advanced engineering applications using C, C++, Java, Labview, and MySQL databases. Responsibilities also include negotiating contracts and managing production runs with various contract manufacturing companies. Other responsibilities include patent applications, network design/support, component purchasing, reverse engineering, competitive analysis, and technical staffing.

Lexmark International (3/7/05 to 8/1/2011 - Lexington, KY)

Sr. ASIC Engineer responsible for device/process modeling, process characterization, standard cell development, and CMOS design methodologies. Using BSIM Pro for semiconductor device modeling and Cadence VSDE/VCME for timing characterization. Developed the CMOS standard cell family that is currently being used for all ink jet print head development. Cells are compatible with the Cadence Encounter place and route system and support Synopsys and Xilinx flows for synthesis. Also using the Coventor SEMulator3D tools for device structure and standard cell analysis. Currently engaged in RCX/ QRC correlation activities using parasitic extraction structures and various circuits for digital performance analysis. Also responsible for parametric process analysis and monitoring using Spotfire/JMP-9 data analysis software, ChipCentric, and custom Process Control Monitor structures. Member of the Lexmark Imaging Solutions & Services Group (ISS) which is responsible for new ink jet print head designs and R&D.

Epicenter Technologies (3/2002 to 6/7/2004 - Huntsville, AL)

Designed a Java based broadband multimedia platform and teamed with five partners to pursue venture capital funding for the project. Developed a complete business plan, product specifications, technical presentations, and marketing support material. Conducted research on product components, Java processors, software APIs, manufacturing resources, and competing technologies. Developed and submitted patent applications and support material as needed. Currently developing a software prototype using the JAVA3D, JOGL, OpenGL, and J2SE APIs. ( See Broadband Multimedia Project for additional information ).

Other areas of interest include Bluetooth wireless technologies, MPEG-4, MIDI, 802.11a/b/g, 3D graphics, gigabit-ethernet, USB 2.0 , and Firewire IEEE 1394. Also exploring the use of embedded Java processors (MAJC, Moon, aJile, TINI, Zucotto & Pico-Java) for telecom, networking, and multimedia applications.

Software interests include Java (J2ME, J2SE, JINI), TCL/TK, and Perl programming. Currently porting several EDA applications to Mac OS-X using the Eclipse and Xcode IDEs. (See Current Projects for details). Coming up to speed on UML and XML development tools.

ADTRAN (Feb 1996 to March 2002 - Huntsville Alabama)

Engineering Manager of ADTRAN's mixed-signal IC development group. Responsibilities at ADTRAN included management of 3rd party mixed-signal design activities, semiconductor foundry procurement, IC design methodologies, EDA tool support, and the development of mixed-signal test systems. I also participated in the development of DDS, ISDN, T1/E1, MDSL, SDSL, HDSL-2, and G.SHDSL transceivers. Designs were implemented using CMOS technologies (MOSIS, AMI, NWL, UMC, & TSMC). Foundry procurement activities included a recent survey of vendors for 0.35u, 0.25u, 0.18u, and 0.15-0.10u CMOS and BICMOS technologies.

Prior to being promoted to Engineering Manager, I was a Senior Staff Scientist within ADTRAN's Technical Staff group. During that time I worked on team oriented projects that led to the commercial release of various SDSL and MDSL products. The projects were a joint development effort with Siemens/Infineon in Munich Germany.

Java activities include a project lead role in the development of a client-server based transmission line analysis system (DSL Assistant). The DSL Assistant program has been ported to Solaris, PC, and Macintosh platforms using the CodeWarrior Java IDE. The application is currently being distributed to ADTRAN customers via their corporate web site (www.adtran.com).

Epicenter Technologies (Nov 1995 - Feb 1996 - Jackson Mississippi )

Worked as an independent consultant providing EDA services, UNIX support, software development services, and web related design services (C++ CGI, Java, & HTML). Customers included Advanced Microelectronics, ADTRAN, ATSI (ISP related), and a secure government agency.

Advanced Microelectronics (July 1990-Nov 1995 - Jackson, Mississippi )

As CAD Section Manager / DoD Program Manager , my responsibilities included CAD tool integration, custom application development, laboratory automation, and Sun network operations. In addition, I was responsible for a team of engineers that developed custom CAD software and integrated circuits for various government agencies. The tools developed by this team (CMOSX cell library) were distributed to over 300 universities and research organizations. I was directly responsible for program proposals that resulted in $9.7 million in new funding for our division. Under these programs I managed teams of 8-14 engineers depending on the nature of the project.

My group completed the development of an automated standard cell development system that was created from the ground up for a secure DoD agency ($2.8 million contract). The system was implemented within the Cadence OPUS design framework. To achieve a high degree of process portability the cells were designed using symbolic primitives that were compacted to create a final layout. An automated slew-rate dependent timing characterization methodology was also developed. The modeling technique generated logic model timing accurate to within 3% of HSPICE simulation results. We also developed software to port this timing data to Verilog, VHDL, and Synopsys models. The modeling methodology also included support for post layout timing back-annotation using the Cadence Central Delay calculator, extracted router parasitics, and Standard Delay Files (SDF). At the conclusion of this project my team was awarded a multi-year $4.5 million contract to develop and maintain the system.

I managed the daily operations of the computer network and developed new strategies for minimizing design cycle times. My team supported an installed base of commercial CAD tools representing a $3.5 million investment in software. The computer network consisted of 35 Sun workstations sharing 5 file servers. My team developed custom software applications using C, C++, and X11R6. Software developers in my group used a structured development environment with software revision control utilities, team oriented development frameworks, and various source code libraries.

Level One Communications (Aug 1987 to July 1990 - Folsom,California )

Employed as a Device Modeling Engineer developing circuit simulation models for CMOS and BIPOLAR devices. Modeling activities were supported by IEEE-488 software driving parametric test equipment from a Vax 11/780 and a Macintosh II. I was responsible for the definition and development of the entire system including low level hardware interfaces. Semiconductor characterization routines were developed using LabView instrument control software and Lightspeed C. Statistical process control databases were implemented on the Macintosh and were used to determine the upper and lower bounds for various device models. Parameter optimization algorithms were used to fit the models to empirical data.

In addition to responsibilities as device modeling engineer I participated in CAD tool development, SUN workstation support, and standard cell design. Foundry related responsibilities include process characterization, verification of electrical specifications, PCM development, failure analysis, and design rule analysis.

TRW LSI Products Division (Feb 1983 to Aug 1987 - San Diego, California )

As Section Manager of the Design Systems Engineering Group I directed the development of software systems which provided interfaces to Mentor CAD tools. I was also responsible for the acquisition, maintenance, and support of all workstation hardware and software. While at TRW I developed systems to monitor semiconductor wafer processing, parameter optimization software for circuit simulation, and simulator interfaces to schematic databases. Applications and simulation models were developed using C, Pascal, Modula-2 and Fortran. In addition, I provided technical support with logic simulation tools, block place and route software, and silicon compilers.

Positions held:
  • Digital Design Engineer
  • CMOS Device Engineer
  • Senior Design Software Engineer
  • Section Manager, Design Systems Engineering

General Electric, Microelectronics Center (Jan 1982 to Feb 1983 - Research Triangle, N.C. )

Hired as a start-up member of the MEC gate array design team participating in all phases of gate array and standard cell design. Primarily involved in CAD tool development, logic cell design, and digital system modeling. The gate-array masters developed by our group were marketed by Intersil, a GE subsidiary.

General Electric, Mobile Radio Department (Jan 1981 to Jan 1982 - Lynchburg, Virginia)

Digital Design Engineer in the CMOS Advance IC Development Group. Responsibilities included characterization of short channel (1u) CMOS processes, standard cell development, and logic verification of digital subsystems for mobile phones, pagers, and radios. Transferred to the MEC design center after completing in-house courses in digital CMOS design.

Education and professional development:

  • BSEE from the University of Kentucky, 1980
  • EIT Registration in Kentucky
  • 1989 CICC co-chairman on simulation and device modeling
  • Various classes in DSP, process modeling, semiconductor device modeling, and VLSI technology
  • Management training courses in team leadership, task management, product development, software development, and software law.

EDA Experience:

  • System Simulation: Ptolemy, StateCAD, QUCStudio
  • Synthesis: Synopsys, Ambit, Xilinx, Altera (VHDL & Verilog)
  • RF Tools Sonnet, EMScan, EMgine, Ettus SDR
  • PCB Tools Eagle, Altium, Sunstone PCB123
  • Cadence Tools Composer, Virtuoso, Spectre, AMS, Encounter P&R. Cell Ensemble, Assura, Diva, Dracula, RCX, QRC
  • Hardare Accelerators: IKOS and Zycad
  • Logic Simulators: Verilog-XL, Quicksim, Silos, Viewlogic, VSS
  • Circuit Simulators: Spectre, HSPICE, Spice3F4, MacSPICE, LTSpice
  • Device Modeling: BsimPro, UTMOST, Coventor SEMulator3D, Spotfire, JMP 9, ChipCentric
  • Layout Editors: Virtuoso, L-Edit, Klayout, Glade, gEDA, Magic, Electric, Calma
  • IC Database/Netlist formats: EDIF, SDF, SPF, RSPF, GDSII, CIF

Software Development:

  • Programming Languages: TCL/TK, C, C++, Java, Objective-C, & VRML
  • Java IDEs & Compilers: Project Builder, Jgrasp, Xcode, Eclipse, NetBeans, CodeWarrior, BlueJ, Dr. Java, HotSpot
  • UNIX/Linux OS Experience: Mac OS-X, Ubuntu, Mint, Solaris, Red Hat Linux, Fedora, Linaro, and BSD. Virtualization using Parallels, Vmware, & VirtualBox
  • UNIX Development: Qt Creator, Eclipse, CenterLine ObjectCenter, GNU compilers, EGCS, Sun Workshop C/C++, Code Crusader, ProjectBuilder
  • X11R6: X11 server installation and configuration including KDE and Gnome environments
  • System Admin: Familiar with many UNIX system admin tasks and configuration requirements
  • Web: Server configuration & installation (MacHTTP, NSCA, Apache, JBoss, Jigsaw, MySQL, Sawmill, Analog, VMWare)
  • CGI: Script development using UNIX shell scripts, C++, and Java
  • IEEE-488 GPIB: Instrument driver development using LabView and LabWindows.
  • Hardware Platforms: Oracle Sparc/Solaris, Macintosh OS-X systems, embedded Linux systems, Via Technologies ITX boards, BeagleBoard, PandaBoard, SheevaPlug, MBed, & Arduino boards
  • Multimedia: Quicktime, Adobe Premiere, MPEG4, MP3 Audio, Bryce, Poser, GIMP, & Adobe Photoshop
  • Audio Production: Logic X, Logic Pro/Studio, Reason, Reaktor 5, Audio Mulch, Line 6 interfaces, Riffworks, & Garageband.